Non-volatile memories are commonly used in several applications when the data stored in the memory device need to be preserved even in absence of a power supply. Within the class of non-volatile memories, electrically programmable (and erasable) memories, such as flash memories, have become very popular in applications in which the data to be stored are not immutable (as it might be in the case of, e.g., a consolidated code for a microprocessor), being instead necessary from time to time to store new data, or to update the data already stored.
Typically, the memory device includes an arrangement of memory cells, disposed for example in rows and columns, so as to form a matrix.
Depending on the way the memory cells in the matrix are interconnected, two classes of flash memories can be identified: those having a so-called NOR architecture, or NOR flash memories, and those having a so-called NAND architecture, shortly referred to as NAND flash memories. Roughly speaking, in a NOR architecture the memory cells of a same matrix column are connected in parallel to a same bit line, whereas in a NAND architecture groups of memory cells of a same matrix column are serially interconnected so as to form respective strings, which strings are then connected in parallel to each other to a same bit line.
Compared to NOR flash memories, NAND flash memories are more compact (a lower number of contacts in the matrix are required), and they are also better suited for applications such as file storage.
In the NAND architecture, the memory space is ideally partitioned into a plurality of memory pages, each page corresponding to a block of memory cells that, in operation, are read or written simultaneously, i.e. in parallel to each other. The number of memory cells in each block determines the size (i.e., the number of bits) of the memory page. Nowadays, memory pages of 512 Bytes are rather typical, but larger memory pages are also encountered, for example of 2 KBytes.
Clearly, the memory cannot have so high a number of Input/Output (I/O) terminals as to enable transferring in parallel such long data words; usually, eight or sixteen I/O terminals are in fact provided; thus, some kind of “segmentation” of the memory page is necessary for interfacing the memory with the outside world.
To this purpose, a circuit arrangement called a “page buffer” is provided in the memory for managing the operations of reading the information stored in the memory cells of a selected memory page, or writing new information thereinto. In very general terms, the page buffer includes a buffer register of size equal to that of the memory page, wherein data read (in parallel) from the memory cells of a selected page are temporarily stored, before being serially outputted in chunks of, e.g., eight or sixteen bits, depending on the number of I/O terminals of the memory; similarly, when data are to be written into the memory, the page buffer is replenished with data received serially in said eight- or sixteen-bits chunks, and, when the buffer has eventually been filled, the data are written in parallel into the memory cells of a given, selected memory page.
The page buffer includes a relatively high number of volatile storage elements, typically bistable elements or latches; the number of latches is proportional (in particular, equal) to the size (in number of bits) of the memory page; thus, the page buffer is a circuit block that needs to be carefully designed (both at the circuit and at the physical layout level), so as to ensure that it does not occupy too large a semiconductor area, and it is efficient, particularly from the power consumption viewpoint.
If the operations to be performed on the memory cells are simply a “PAGE READ” (an operation involving reading data from a selected memory page) and a page write or “PAGE PROGRAM” (writing data into a selected memory page), the page buffer may in principle include a single register, with a number of latches equal to the size (in bits) of the memory pages. However, more complex operations may be desirable and required, and in these cases the structure of the page buffer may need to be upgraded. For example, in some applications it might be necessary that the memory is capable of performing operations such as a “COPY-BACK PROGRAM” and a “CACHE PROGRAM”. In a CACHE PROGRAM operation, data to be written into a memory page can be loaded into the page buffer while another memory page is still being written with data loaded in the page buffer at a previous time; in this way, the time necessary for programming in sequence different memory pages is reduced. A COPY-BACK PROGRAM operation is instead exploited for copying the data contained in a given memory page into another memory page, in a way managed completely internally to the memory, without the necessity of outputting the data. A page buffer adapted to implement these two additional operations needs to include a pair of buffer registers (and thus two arrays of latches), that can be coupled to two selectable packets of bit lines of the matrix.
Typically, the page buffer includes two registers, a main register and a cache register, each one controlled by respective control signals and having different functions. In detail, the cache register is not used in the PAGE READ operation (which is performed using only the main register) and is not adapted to perform writing operations; the cache register is exploited for loading data to be programmed into, or read from, selected memory cells. On the contrary, the main register is adapted to program selected memory cells; the main register receives the data from the cache register and, then, performs the required writing operation. In the CACHE PROGRAM operation such a structure permits to program a first memory page by means of the main register while the data to be written into a second memory page are loaded into the cache register, thus speeding up the operation. In the COPY-BACK PROGRAM operation data are loaded from a given page into the cache register, transferred from the cache register into the main register and then programmed in another page by the main register.
However, a phase of data transfer from the cache register into the main register is necessary, and an increasing request for faster NAND memories has brought to devise solutions for further speeding up the operations to be performed.
For example, U.S. Published Patent Application No. 2003/0076719 discloses a page buffer including two sense and latch blocks, which exclusively carry out the same function. While one of the sense and latch blocks carries out a read operation, the other sense and latch block outputs previously sensed data to the exterior. Further, while one of the sense and latch blocks carries out a program operation, the other sense and latch block loads data to be programmed. In detail, the two sense and latch blocks include a latch, a transfer circuit for reading operation and a transfer circuit for programming operation, respectively. The reading transfer circuit is adapted to load a data bit, read from the selected memory cell or received from the I/O terminals of the memory, into the latch and to output the read data bit towards the I/O terminals of the memory. The programming transfer circuit is adapted to program the selected memory cell accordingly to the received data bit.
The latch included in the two registers of the page buffer must be reset before a reading operation. A reset of the latches in the two sense and latch blocks is described in U.S. Published Patent Application No. 2003/0076719 and is obtained by exploiting a precharge circuit and a three-transistor path included in the reading transfer circuit and controlled by three corresponding control signals. Furthermore, a data loading and a data outputting performed by the reading transfer circuit require a two-transistor path controlled by two corresponding control signals.
The Applicant observes that the control of the reset of the latch and of the data loading and outputting is critical, since it depends on a plurality of control signals corresponding to a respective multitude of transistors. In addition, the two-transistor path for loading/outputting data consists of two N-channel MOS transistors in series, which typically do not effectively transfer voltage signals corresponding to the high logic level.
Furthermore, the programming transfer circuit is described including a three-state buffer controlled by a corresponding signal. The Applicant observes that the three-state buffer of the programming transfer circuit includes four transistors and this is contrary to the desire of saving occupied area. This is a substantial waste of occupied area considering that there is one programming transfer circuit for each sense and latch block, and that the number of sense and latch blocks in the memory is equal to the memory page size (typically ranging from 512 byte and 2 kbyte).
In view of the state of the art outlined in the foregoing, the Applicant has faced the problem of providing a fast page buffer, occupying a limited area and controllable in a simpler way.